Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
The channel length of a floating gate flash memory cell refers to the length of the substrate region between source and drain junctions that is controlled by the memory cell's floating gate. In order to increase the memory density of memory devices, the physical channel length can be shortened to fit more memory cells within a certain area of real estate. The effective channel length may also be shortened as a result of undesirable electrical characteristics of memory cells.
As the channel length of a memory cell decreases, either physically or effectively, the source and drain regions of the memory cell become effectively closer to each other. This can cause undesirable short channel effects. For example, a short channel effect known as “punch through” occurs when a high drain voltage causes uncontrolled current (i.e., current that is not controlled by the memory cell's floating gate) to flow. Drain induced barrier lowering (“DIBL”) is another undesirable short channel effect that can occur when effective channel length decreases. As a result of DIBL, the memory cell's effective threshold voltage decreases which undesirably affects the performance of the memory cell.
FIGS. 1A and 1B illustrate a typical prior art read operation. FIG. 1A shows the prior art read operation of a memory cell 100 at word line WLn. In this example, the memory cells 101, 103 at WLn−1 and WLn+1 are assumed to be programmed. A representation of the effective channel length 110 is shown under the WLn memory cell 100.
FIG. 1B shows the prior art read operation of a memory cell 121 on WLn in which the adjacent memory cells 120, 122 on WLn−1 and WLn+1 are erased. The representation of the effective channel length 120 is shown as being substantially shorter than that of the programmed adjacent memory cells of FIG. 1A. Thus, erased adjacent memory cells can result in a shorter effective channel length during a read operation.
One method that has been used to reduce the effects of the shorter effective channel length is typically referred to as the corrective read operation. The corrective read method involves dynamically changing only the WLn bias during the read operation to compensate for floating gate-to-floating gate shift. One problem with this method is that it does not compensate for floating gate-to-floating gate coupling variations.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art to reduce the effects of erased memory cells during a sense operation.